[Libre-soc-bugs] [Bug 1146] use separate computer instead of ddr3 for fpga memory interface for now

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1146

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #0)

> I was thinking we'd create a simple wishbone interface that translates
> memory accesses to uart messages and communicates with the computer, since
> uarts can run at multiple mhz.

HyperRAM is much simpler and there is the advantage that models of
the actual HyperRAM ICs are available.  cocotb can be used to create
a compatible software variant that is checked against the model.

or, nuts to it: much simpler protocols barely above what wishbone
is can also be written. at some point we do need an inter-memory
protocol, to connect FPGAs together. this would be a step in that
direction.

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