[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1039

--- Comment #33 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
+        if self.stages[0] is None: return stall
+
+        insn, writeregs = self.stages[0]
+        self.cpu.exe.add_instruction(insn, writeregs)

generally if you're going to do that you might as well do:

+        if self.stages[0] is None:
+             return stall
+        insn, writeregs = self.stages[0]
+        self.cpu.exe.add_instruction(insn, writeregs)

personally i quite like the style of putting single-line ifs,
but pep8 bitches about it, and autopep8 will change it, which
gives you some indication of how uncommon it is, and therefore
it's risky from a maintenance perspective
(Principle of Least Surprise)

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