[Libre-soc-bugs] [Bug 1039] add hardware-cycle-accurate stastistical modelling to ISACaller for an in-order core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1039

--- Comment #24 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Andrey Miroshnikov from comment #22)


> because the execute object's 'add_stage' method seems

not "seems": DOES.

>  to add the extra 2
> cycle
> delay.

this is 100% correct and 100% intended. do not alter it, fix the
previous stage so that the transfer from decode to issue is on
a 1 cycle delay. that is the source of the error.

later on, DIV will not be 2 cycles, will it?

A DIV operation is variable-length, isn't it?


(In reply to Andrey Miroshnikov from comment #23)

> Missed the second commit:
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=755b918d6dad6fc2d1a2a75beb1fdd39223679c7

please revert.

execute must have multiple operations outstanding (and an additional piece of
output indicating the countdown)

this is a superscalar architecture.

otherwise when DIV operations take 128 clock cycles to complete, 128 execute
columns will be needed, won't they?

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