[Libre-soc-bugs] [Bug 1125] split instructions' pseudo-code into separate files so they can be [[!inline]]-ed into the wiki

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1125

--- Comment #7 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)
> (In reply to Jacob Lifshay from comment #5)
> > and because the way instructions' different
> > parts are organized in rfcs don't match how the parser likes them (e.g. we
> > have the instruction form as a textual table, as well as having the full
> > description text). if we do want the whole instruction split out per file,
> > we still need just the pseudo-code in a separate file for the above reasons.
> 
> no: the way i would like it done is that the RFCs *include the entire
> instruction* and if the RFC is different the *instruction* is modified
> (and the parser to match) to cope.

ok, how about this:

we have the entire RFC instruction entry in e.g.
openpower/isa/bitmanip/sadduw.mdwn and have the pseudo-code separated out into
openpower/isa/bitmanip/sadduw_code.mdwn.

the pseudocode would be in a file by itself for those cases where we want just
the pseudocode in the wiki, such as:
https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/bitmanip.mdwn;h=5c84e83e5912844d771488ac875921f787accf40;hb=4925f0c8f5a166c6ecb9528d60ab943280287c6e#l278

it would look like so (file contents indented by 4 extra spaces for clarity):

ls004.mdwn:
    <snip>

    \newpage{}

    [[!inline pagenames="openpower/isa/bitmanip/sadduw" raw="yes"]]

    # Instruction Formats

    <snip>

openpower/isa/bitmanip.mdwn:
    <!-- Draft Instructions here described in -->
    <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
    <!-- These instructions are *not yet official* -->

    <snip>
    [[!inline pagenames="openpower/isa/bitmanip/sadduw" raw="yes"]]

openpower/isa/bitmanip/sadduw.mdwn:
    # Shift-and-Add Unsigned Word

    `sadduw RT, RA, RB, SH`

    |  0-5  | 6-10 | 11-15 | 16-20 | 21-22 | 23-30 | 31 | Form     |
    |-------|------|-------|-------|-------|-------|----|----------|
    |  PO   | RT   |  RA   |  RB   |  SH   |  XO   | Rc | Z23-Form |

    Pseudocode:

    ```
    [[!inline pagenames="openpower/isa/bitmanip/sadduw_code" raw="yes"]]
    ```

    When `SH` is zero, the lower word contents of register RB <snip>

openpower/isa/bitmanip/sadduw_code.mdwn:
(note additional indent-4 that's actually in file, beyond indent-4 for this
comment)
        shift <- SH + 1                  # Shift is between 1-4
        n <- (RB)[32:63]                 # Only use lower 32-bits of RB
        sum[0:63] <- (n << shift) + (RA) # Shift n, add RA
        RT <- sum                        # Result stored in RT

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