[Libre-soc-bugs] [Bug 1127] Generating a Libre-SOC Microwatt-compatible core with SVP64

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1127

--- Comment #1 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
Created attachment 196
  --> https://bugs.libre-soc.org/attachment.cgi?id=196&action=edit
Shows full log of ls2 synthesis

Next step was to place the generated core inside the ls2 peripheral framework
and create an FPGA image.
During the yosys synthesis, I encountered many combinatorial loops, which
caused the timing analysis to fail. The errors mostly occurred in dec2,
specifically the sv blocks.
Full log is attached.

-- 
You are receiving this mail because:
You are on the CC list for the bug.