[Libre-soc-bugs] [Bug 1127] New: Generating a Libre-SOC Microwatt-compatible core with SVP64

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1127

            Bug ID: 1127
           Summary: Generating a Libre-SOC Microwatt-compatible core with
                    SVP64
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
               URL: https://libre-soc.org/HDL_workflow/ls2/
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: andrey at technepisteme.xyz
          Reporter: andrey at technepisteme.xyz
                CC: libre-soc-bugs at lists.libre-soc.org, lkcl at lkcl.net
        Depends on: 1086
            Blocks: 961
   NLnet milestone: NLnet.2022-08-107.ongoing

Created attachment 195
  --> https://bugs.libre-soc.org/attachment.cgi?id=195&action=edit
Diff of mw vs mw+svp64 core using yosys ls

Last Thursday I started looking into generating an external Libre-SOC core
containing SVP64 (no elwidth overrides, 64-bit element width only), while also
retaining Microwatt compatibility (so that we could run the same binary).
https://libre-soc.org/irclog/%23libre-soc.2023-07-27.log.html#t2023-07-27T18:03:34

(I do apologise for not raising the bug report earlier and misusing the IRC.
For anyone seeing this in the future, please see bug #1126 for how to properly
report an issue.)

The core is generated from the soc repo, by calling the Makefile. I'm using the
environment produced by following the ls2 setup on the wiki page.

I added a rule to the Makefile, and an argument to issuer_verilog.py, leaving
all the parameters the same as 'microwatt_external_core', except setting
'svp64' to True.
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=7c41d80d9a1af94f8dacd808b822bee62a620811

When running 'make microwatt_external_core_svp64', I hit an AttributeError,
with PowerDecode2 missing the signal 'use_svp64_ldst_dec'.

On Monday I looked at the commits in openpower-isa (that's where the
power_decoder2.py is located). See:
https://libre-soc.org/irclog/%23libre-soc.2023-07-31.log.html#t2023-07-31T13:44:10

This commit on 24th June 2021 shows the 'use_svp64_ldst_dec' signal being
added):
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=847075a69e38b96376b7db0d5df0cc125da0be7a

A commit on the 12th August 2022 then removes this signal:
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=fdba782098076205d7740fc091d925d63b29a194

Using openpower-isa commit #1bbfcce929c9a1d6b1dc0fc68c84296bcc58eea1 (the one
before the signal was removed), I was able to generate an external core with
the SVP64 enabled.
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=1bbfcce929c9a1d6b1dc0fc68c84296bcc58eea1

To make sure the SVP64 related blocks are really there, I loaded the verilog
file into yosys and listed the modules using ls. The diff comparing the
Microwatt-compatible and MW+SVP64 is included as a text file.

Next step is to test the core within ls2.


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=961
[Bug 961] NLnet 2022 Libre-SOC "ongoing" milestone 2022-08-107 (approved, MoU
TBD)
https://bugs.libre-soc.org/show_bug.cgi?id=1086
[Bug 1086] ls2 verilator sim - setting up chroot and documentation
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