[Libre-soc-bugs] [Bug 976] support missing specifiers

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=976

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #12)
> As for r30/30/*/%, here's that discussion:
> https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-June/004996.html
> 
> We already iterated through this. Either -regnames, or explicit registers. I
> think this might work with `.set pred,%r30`. But in predicates it always
> tries to look for register names.

that means pysvp64asm needs to support it too.  much as i don't like %
it's an ok path to get things to work

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