[Libre-soc-bugs] [Bug 890] Static Timing Analysis of eth_mac

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=890

--- Comment #48 from Marie-Minerve Louerat <marie-minerve.louerat at lip6.fr> ---
Comparison results of Static Timing Analysis (HiTas) and transistor-level
simulation using an NDA 180nm cmos technology. 

Use case: C4M-FlexLib inverter and inverter chain
showing how to configure the tools and provide results.

Evaluation results could be rebuilt with :

  * alliance-check-toolkit commit #6d03d407

and your NDA-PDK.

Inverter Analysis
--------------------

A. With STA
++++++++++++
Running:

1. Building the timing database
   ./hitas/db.tcl

NB. here, Hitas uses inv_x2_hitas.spi description of the netlist 
to detect VDD and VSS
(see inv_x2.rep)

2. Report critical paths
   ./hitas/report_inv.tcl

provides the inv_x2.paths file that shows the 2 paths of the inverter.

+-------+--------+--------------+-----------------------+
| input | output | input slope  |  propagation delay
+=======+========+==============+=======================+
| F     | R      | 5            |  NDA
+-------+--------+--------------+-----------------------+
| R     | F      | 5            |  NDA
+-------+--------+--------------+-----------------------+

where F: falling, R: rising.

B. With transistor level simulator eldo (Siemens EDA software)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

eldo top_eldo.spi
displays the delays (input slope and propagation delay) 
and write them in the file top_eldo.chi
and
ezwave
displays timing plots 

+-------+--------+--------------+-----------------------+
| input | output | input slope  |  propagation delay
+=======+========+==============+=======================+
| F     | R      | 5            |  NDA
+-------+--------+--------------+-----------------------+
| R     | F      | 5            |  NDA
+-------+--------+--------------+-----------------------+


where F: falling, R: rising, timing results.

showing that STA delays are greater than simulation delays,  
keeping the relative order,
with an error for STA of : 6% in the worse case.

Inverter chain timing analysis
------------------------------

A. With STA
++++++++++++
Running:

1. Building the timing database
   ./hitas/db_chain.tcl

NB. Here, Hitas uses inv_x2_chain_hitas.spi description of the netlist 
to detect VDD and VSS
(see inv_x2_chain.rep)


2. Report critical paths
   ./hitas/report_chain.tcl

provides the inv_x2_chain.paths file that shows the 2 paths of the inverter
chain.

+-------+--------+--------------+-----------------------+
| input | output | input slope  |  propagation delay
+=======+========+==============+=======================+
| F     | R      | 5            |  NDA
+-------+--------+--------------+-----------------------+
| R     | F      | 5            |  NDA
+-------+--------+--------------+-----------------------+

where F: falling, R: rising, timing results.

3. Other analysis with the Hitas GUI: Xtas
   xtas
   file/open inv_x2_chain.dtx
   Tools/Get Paths
   Select path/path Detail

B. With transistor level simulator eldo (Siemens EDA software)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

eldo top_chain_eldo.cir
displays the delays (input slope and propagation delay) 
and write them in the file top_chain_eldo.chi
and
ezwave
displays timing plots 

+-------+--------+--------------+-----------------------+
| input | output | input slope  |  propagation delay
+=======+========+==============+=======================+
| F     | R      | 5            |  NDA
+-------+--------+--------------+-----------------------+
| R     | F      | 5            |  NDA
+-------+--------+--------------+-----------------------+

where F: falling, R: rising, timing results.

showing that STA delays are slightly smaller than simulation delays, 
keeping the relative order, 
with an error for STA of : 4% in the worse case.

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