[Libre-soc-bugs] [Bug 890] Static Timing Analysis of eth_mac

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=890

--- Comment #44 from Marie-Minerve Louerat <marie-minerve.louerat at lip6.fr> ---
Comparison results of Static Timing Analysis (HiTas) and transistor-level
simulation (ngspice) using the cmos Sky130 technology. 

Use case: inverter and inverter chain
showing how to configure the tools and provide results.

Evaluation results could be rebuilt with :

  * alliance-check-toolkit commit #6d03d407

Inverter timing analysis
-------------------------
A. With STA
++++++++++++
Running:

1. Building the timing database
   ./hitas/db_ng.tcl

NB. here, Hitas uses inv_x2_hitas.spi description of the netlist 
to detect VDD and VSS
(see inv_x2.rep)

2. Report critical paths
   ./hitas/report_inv_ng.tcl

provides the inv_x2.paths file that shows the 2 paths of the inverter.

+-------+--------+--------------+-----------------------+
| input | output | input slope  |  propagation delay
+=======+========+==============+=======================+
| F     | R      | 8            |  10
+-------+--------+--------------+-----------------------+
| R     | F      | 8            |  8 
+-------+--------+--------------+-----------------------+

where F: falling, R: rising, timing results in ps.

B. With transistor level simulator ngspice
++++++++++++++++++++++++++++++++++++++++++

ngpsice top_inv_x2.spi
displays timing plots with information of input slope and propagation delay :

+-------+--------+--------------+-----------------------+
| input | output | input slope  |  propagation delay
+=======+========+==============+=======================+
| F     | R      | 8            |  7.15
+-------+--------+--------------+-----------------------+
| R     | F      | 8            |  6.95
+-------+--------+--------------+-----------------------+

where F: falling, R: rising, timing results in ps.
showing that STA delays are greater than transistor simulation delays,  
keeping the relative order,
with an error for STA of : 28% in the worse case.

Inverter chain timing analysis
------------------------------

A. With STA
++++++++++++
Running:

1. Building the timing database
   ./hitas/db_chain_ng.tcl

NB. Here, Hitas uses inv_x2_chain_hitas.spi description of the netlist 
to detect VDD and VSS
(see inv_x2_chain.rep)

2. Report critical paths
   ./hitas/report_chain_ng.tcl

provides the inv_x2_chain.paths file that shows the 2 paths of the inverter
chain.

+-------+--------+--------------+-----------------------+
| input | output | input slope  |  propagation delay
+=======+========+==============+=======================+
| F     | R      | 8            |  93
+-------+--------+--------------+-----------------------+
| R     | F      | 8            |  89
+-------+--------+--------------+-----------------------+

where F: falling, R: rising, timing results in ps.

3. Other analysis with the Hitas GUI: Xtas
   xtas
   file/open inv_x2_chain.dtx
   Tools/Get Paths
   Select path/path Detail

B. With transistor level simulator ngspice
++++++++++++++++++++++++++++++++++++++++++

ngpsice top_inv_x2_chain.spi
displays timing plots with information of input slope and propagation delay :

+-------+--------+--------------+-----------------------+
| input | output | input slope  |  propagation delay
+=======+========+==============+=======================+
| F     | R      | 8            |  87
+-------+--------+--------------+-----------------------+
| R     | F      | 8            |  85
+-------+--------+--------------+-----------------------+

showing that STA delays are greater than simulation delays, 
keeping the relative order, 
with an error for STA of : 6% in the worse case.

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