[Libre-soc-bugs] [Bug 890] Static Timing Analysis of eth_mac

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=890

--- Comment #40 from Marie-Minerve Louerat <marie-minerve.louerat at lip6.fr> ---
Comparison results of Static Timing Analysis (HiTas) and transistor-level
simulation (ngspice) using a "dummy" cmos technology. 

Use case: invertoer and inverter chain
showing how to configure the tools and provide results.

Evaluation results could be rebuilt with :

  * alliance-check-toolkit commit #6d03d407

Inverter timing analysis
-------------------------

A. With STA
++++++++++++
Running:

1. Building the timing database
   ./hitas/db_ng.tcl

NB. here, Hitas uses inv.spi description of the netlist 
to detect VDD and VSS
(see inv.rep)

2. Report critical paths
   ./hitas/report_inv_ng.tcl

provides the inv.paths file that shows the 2 paths of the inverter.

+-------+--------+--------------+-----------------------+
| input | output | input slope  |  propagation delay
+=======+========+==============+=======================+
| F     | R      | 20           |  51
+-------+--------+--------------+-----------------------+
| R     | F      | 20           |  40 
+-------+--------+--------------+-----------------------+

where F: falling, R: rising, timing results in ps.

B. With transistor level simulator ngspice
++++++++++++++++++++++++++++++++++++++++++

ngpsice top_inv.spi
displays timing plots with information of input slope and propagation delay :

+-------+--------+--------------+-----------------------+
| input | output | input slope  |  propagation delay
+=======+========+==============+=======================+
| F     | R      | 20           |  36 
+-------+--------+--------------+-----------------------+
| R     | F      | 20           |  30 
+-------+--------+--------------+-----------------------+

where F: falling, R: rising, timing results in ps.
showing that STA delays are greater than simulation delays,  
keeping the relative order,
with an error for STA of : 30% in the worse case.

Inverter chain timing analysis
------------------------------

A. With STA
++++++++++++
Running:

1. Building the timing database
   ./hitas/db_chain_ng.tcl

NB. here, Hitas uses inv_chain.spi description of the netlist 
to detect VDD and VSS
(see inv_chain.rep)

2. Report critical paths
   ./hitas/report_chain_ng.tcl

provides the inv_chain.paths file that shows the 2 paths of the inverter chain.

+-------+--------+--------------+-----------------------+
| input | output | input slope  |  propagation delay
+=======+========+==============+=======================+
| F     | R      | 20           |  439 
+-------+--------+--------------+-----------------------+
| R     | F      | 20           |  397
+-------+--------+--------------+-----------------------+

where F: falling, R: rising, timing results in ps.

3. Other analysis with the Hitas GUI: Xtas
   xtas
   file/open inv_chain.dtx
   Tools/Get Paths
   Select path/path Detail

B. With transistor level simulator ngspice
++++++++++++++++++++++++++++++++++++++++++

ngpsice top_inv_chain.spi
displays timing plots with information of input slope and propagation delay :

+-------+--------+--------------+-----------------------+
| input | output | input slope  |  propagation delay
+=======+========+==============+=======================+
| F     | R      | 20           |  395
+-------+--------+--------------+-----------------------+
| R     | F      | 20           |  377
+-------+--------+--------------+-----------------------+

showing that STA delays are greater than simulation delays, 
keeping the relative order, 
with an error for STA of : 10% in the worse case.

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