[Libre-soc-bugs] [Bug 934] Evaluation of optimized placement for Yosys generated SRAM

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=934

--- Comment #2 from Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> ---
Evaluation results could be rebuild with:

* coriolis commit #d294a770
* alliance-check-toolkit commit #1049f10


Provisional results
~~~~~~~~~~~~~~~~~~~

.. note:: All length are in micro-meters.

+--------------+-----------------------------+-----------------------------+
| Kind         | Generator                   | Yosys                       |
+==============+=============================+=============================+
| # Gates      | 23209      (-25.4%)         | 32121                       |
+--------------+-----------------------------+-----------------------------+
|                                  1 Fold                                  |
+--------------+-----------------------------+-----------------------------+
| Area         | 7182 x 330  (-5.5%)         | 7380 x 340                  |
+--------------+-----------------------------+-----------------------------+
| Wirelength   | 1841036     (-4.3%)         | 1924153                     |
+--------------+-----------------------------+-----------------------------+
|                                  2 Fold                                  |
+--------------+-----------------------------+-----------------------------+
| Area         | 3599 x 660  (-5.3%)         | 3690 x 680                  |
+--------------+-----------------------------+-----------------------------+
| Wirelength   | 1670455     (-6.3%)         | 1782558                     |
+--------------+-----------------------------+-----------------------------+
|                                  4 Fold                                  |
+--------------+-----------------------------+-----------------------------+
| Area         | 1812 x 1320 (-4.6%)         | 1900 x 1320                 |
+--------------+-----------------------------+-----------------------------+
| Wirelength   | 1699810     (-1.5%)         | 1726436                     |
+--------------+-----------------------------+-----------------------------+

Conclusions that we can draw from those results are :

1. The generator version uses subtantially less gates than the Yosys one.
   As the both SRAM uses the exact same number of SFFs, the difference is
   only due to the decoder for the control of input and output muxes.

2. Notwithanding having less gates the generator version uses similar areas,
   which means that we use fewer but significantly *bigger* cells.

3. The FlexLib library supplied for SkyWater 130nm do not contains all
   SxLib one, effectively restricting our choices.

   In particular, to build the output multiplexer we only have mx2 and
   mx3 cells, which are large. The density of the SRAM could be much
   increased if we did have nmx2 and nmx3. We could also try to synthesise
   the tree using nandX and norX but we are short of time.

   Furthermore for the output multiplexers, as it is a controlled case,
   we may also uses three-state drivers cells (which have not been
   ported either).

.. note:: Cell width in the SkyWater 130 port of FlexLib:

          ==============  =====
          Cell            Width
          ==============  =====
          mx2_x2          7
          mx3_x2          11
          nand2_x0        2
          nand3_x0        3
          nand4_x0        4
          nor2_x0         2
          ==============  =====

          1. mx2_x2 + mx3_x2         = 18
          2. 9 * nand2_x0            = 18
          3. 4 * nand3_x0 + nand4_x0 = 16
          4. 6 * nand2_x0 + nor2_x0  = 14

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