[Libre-soc-bugs] [Bug 917] pysvp64dis: support SVP64 disassembly
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Thu Oct 6 12:01:35 BST 2022
https://bugs.libre-soc.org/show_bug.cgi?id=917
--- Comment #78 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
cat /tmp/test.s
sv.cmp/ff=RC1 *0,1,*4,3
cat /tmp/test.s && \
SILENCELOG=true pysvp64asm /tmp/test.s /tmp/test.py.s && \
powerpc64le-linux-gnu-as /tmp/test.py.s -o /tmp/test.o && \
powerpc64le-linux-gnu-objcopy -Obinary /tmp/test.o /tmp/bin.o && \
pysvp64dis -v /tmp/bin.o
sv.cmp/ff=RC1 *0,1,*4,3
09 24 40 05 sv.cmp *0,1,*r4,r3
00 18 21 7c
spec
sv.cmp BF,L,RA,RB
pcode
if L = 0 then
a <- EXTS((RA)[XLEN/2:XLEN-1])
b <- EXTS((RB)[XLEN/2:XLEN-1])
else
a <- (RA)
b <- (RB)
if a < b then c <- 0b100
else if a > b then c <- 0b010
else c <- 0b001
CR[4*BF+32:4*BF+35] <- c || XER[SO]
binary
[0:8] 00000101
[8:16] 01000000
[16:24] 00100100
[24:32] 00001001
[32:40] 01111100
[40:48] 00100001
[48:56] 00011000
[56:64] 00000000
opcodes
011111---------------0000000000-
BF (vector)
00000
38, 39, 40, 19, 20, {0}, {0}
extra3[0]
L
1
42
RA (vector)
0000100
43, 44, 45, 46, 47, 22, 23
extra3[1]
RB (scalar)
00011
48, 49, 50, 51, 52
extra3[2]
RM
None
RM
000000000010010000001001
6, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
25, 26, 27, 28, 29, 30, 31
RM.mmode
0
6
RM.mask
000
8, 10, 11
RM.elwidth
00
12, 13
RM.ewsrc
00
14, 15
RM.subvl
00
16, 17
RM.mode
01001
27, 28, 29, 30, 31
RM.smask
000
24, 25, 26
RM.extra
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.extra2
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.extra2.idx0
10
18, 19
RM.extra2.idx1
01
20, 21
RM.extra2.idx2
00
22, 23
RM.extra2.idx3
00
24, 25
RM.extra3
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.extra3.idx0
100
18, 19, 20
RM.extra3.idx1
100
21, 22, 23
RM.extra3.idx2
000
24, 25, 26
RM.SNZ
0
15
RM.simple
000000000010010000001001
6, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
25, 26, 27, 28, 29, 30, 31
RM.simple.mmode
0
6
RM.simple.mask
000
8, 10, 11
RM.simple.elwidth
00
12, 13
RM.simple.ewsrc
00
14, 15
RM.simple.subvl
00
16, 17
RM.simple.mode
01001
27, 28, 29, 30, 31
RM.simple.smask
000
24, 25, 26
RM.simple.extra
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.simple.extra2
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.simple.extra2.idx0
10
18, 19
RM.simple.extra2.idx1
01
20, 21
RM.simple.extra2.idx2
00
22, 23
RM.simple.extra2.idx3
00
24, 25
RM.simple.extra3
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.simple.extra3.idx0
100
18, 19, 20
RM.simple.extra3.idx1
100
21, 22, 23
RM.simple.extra3.idx2
000
24, 25, 26
RM.simple.SNZ
0
15
RM.simple.RG
1
28
RM.simple.dz
0
30
RM.simple.sz
1
31
RM.mr
000000000010010000001001
6, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
25, 26, 27, 28, 29, 30, 31
RM.mr.mmode
0
6
RM.mr.mask
000
8, 10, 11
RM.mr.elwidth
00
12, 13
RM.mr.ewsrc
00
14, 15
RM.mr.subvl
00
16, 17
RM.mr.mode
01001
27, 28, 29, 30, 31
RM.mr.smask
000
24, 25, 26
RM.mr.extra
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.mr.extra2
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.mr.extra2.idx0
10
18, 19
RM.mr.extra2.idx1
01
20, 21
RM.mr.extra2.idx2
00
22, 23
RM.mr.extra2.idx3
00
24, 25
RM.mr.extra3
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.mr.extra3.idx0
100
18, 19, 20
RM.mr.extra3.idx1
100
21, 22, 23
RM.mr.extra3.idx2
000
24, 25, 26
RM.mr.SNZ
0
15
RM.mr.RG
1
28
RM.mr.dz
0
30
RM.mr.sz
1
31
RM.ff3
000000000010010000001001
6, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
25, 26, 27, 28, 29, 30, 31
RM.ff3.mmode
0
6
RM.ff3.mask
000
8, 10, 11
RM.ff3.elwidth
00
12, 13
RM.ff3.ewsrc
00
14, 15
RM.ff3.subvl
00
16, 17
RM.ff3.mode
01001
27, 28, 29, 30, 31
RM.ff3.smask
000
24, 25, 26
RM.ff3.extra
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.ff3.extra2
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.ff3.extra2.idx0
10
18, 19
RM.ff3.extra2.idx1
01
20, 21
RM.ff3.extra2.idx2
00
22, 23
RM.ff3.extra2.idx3
00
24, 25
RM.ff3.extra3
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.ff3.extra3.idx0
100
18, 19, 20
RM.ff3.extra3.idx1
100
21, 22, 23
RM.ff3.extra3.idx2
000
24, 25, 26
RM.ff3.SNZ
0
15
RM.ff3.VLi
1
28
RM.ff3.inv
0
29
RM.ff3.CR
01
30, 31
RM.ff3.zz
0
14
RM.ff3.sz
0
14
RM.ff3.dz
0
14
RM.ff5
000000000010010000001001
6, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
25, 26, 27, 28, 29, 30, 31
RM.ff5.mmode
0
6
RM.ff5.mask
000
8, 10, 11
RM.ff5.elwidth
00
12, 13
RM.ff5.ewsrc
00
14, 15
RM.ff5.subvl
00
16, 17
RM.ff5.mode
01001
27, 28, 29, 30, 31
RM.ff5.smask
000
24, 25, 26
RM.ff5.extra
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.ff5.extra2
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.ff5.extra2.idx0
10
18, 19
RM.ff5.extra2.idx1
01
20, 21
RM.ff5.extra2.idx2
00
22, 23
RM.ff5.extra2.idx3
00
24, 25
RM.ff5.extra3
100100000
18, 19, 20, 21, 22, 23, 24, 25, 26
RM.ff5.extra3.idx0
100
18, 19, 20
RM.ff5.extra3.idx1
100
21, 22, 23
RM.ff5.extra3.idx2
000
24, 25, 26
RM.ff5.SNZ
0
15
RM.ff5.VLi
1
28
RM.ff5.inv
0
29
RM.ff5.dz
0
30
RM.ff5.sz
1
31
--
You are receiving this mail because:
You are on the CC list for the bug.
More information about the libre-soc-bugs
mailing list