[Libre-soc-bugs] [Bug 950] pysvp64asm: support insndb-based assembly for SVP64 instructions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=950

--- Comment #4 from Dmitry Selyutin <ghostmansd at gmail.com> ---
I've started support for ff/pr/m/sm/dm. These are complicated, for now I've
almost done ff/pr chunks; I'll likely split that huge specifier class into two
or will introduce some base class, since all of these rely on predicates. Below
is an example of how it works (there's an error in binutils, ignore it for now,
I'll fix it later).

$ cat /tmp/test.s && INSNDB=true SILENCELOG=true pysvp64asm /tmp/test.s
/tmp/py.s && echo "### PYSVP64ASM ###" && cat /tmp/py.s && echo "### BINUTILS
###" && powerpc64le-linux-gnu-as -mlibresoc /tmp/py.s -o /tmp/test.o &&
powerpc64le-linux-gnu-objcopy -Obinary /tmp/test.o /tmp/bin.o &&
powerpc64le-linux-gnu-objdump -dr -Mlibresoc /tmp/test.o && echo "###
PYSVP64DIS ###" && time pysvp64dis /tmp/bin.o 
sv.add./dw=32/sw=8/ff=eq *122,56,*3
sv.add./dw=32/sw=8/ff=un *122,56,*3
sv.add/dw=32/sw=8/ff=RC1 *122,56,*3
sv.add/dw=32/sw=8/ff=~RC1 *122,56,*3
### PYSVP64ASM ###
.long 0x054731EA; .long 0x7FD80215; # add./dw=32/sw=8/ff=eq *122,56,*3 #
sv.add./dw=32/sw=8/ff=eq *122,56,*3
.long 0x054731EB; .long 0x7FD80215; # add./dw=32/sw=8/ff=un *122,56,*3 #
sv.add./dw=32/sw=8/ff=un *122,56,*3
.long 0x054731E9; .long 0x7FD80214; # add/dw=32/sw=8/ff=RC1 *122,56,*3 #
sv.add/dw=32/sw=8/ff=RC1 *122,56,*3
.long 0x054731ED; .long 0x7FD80214; # add/dw=32/sw=8/ff=~RC1 *122,56,*3 #
sv.add/dw=32/sw=8/ff=~RC1 *122,56,*3
### BINUTILS ###

/tmp/test.o:     file format elf64-powerpcle


Disassembly of section .text:

0000000000000000 <.text>:
   0:   ea 31 47 05     sv.add./ff=eq/dw=32/sw=8 *r122,r56,*r3
   4:   15 02 d8 7f 
   8:   eb 31 47 05     sv.add./ff=so/dw=32/sw=8 *r122,r56,*r3
   c:   15 02 d8 7f 
  10:   e9 31 47 05     sv.add/ff=gt/dw=32/sw=8 *r122,r56,*r3
  14:   14 02 d8 7f 
  18:   ed 31 47 05     sv.add/ff=le/dw=32/sw=8 *r122,r56,*r3
  1c:   14 02 d8 7f 
### PYSVP64DIS ###
ea 31 47 05    sv.add./dw=32/ff=eq/sw=8 *r122,r56,*r3
15 02 d8 7f    
eb 31 47 05    sv.add./dw=32/ff=so/sw=8 *r122,r56,*r3
15 02 d8 7f    
e9 31 47 05    sv.add/dw=32/ff=RC1/sw=8 *r122,r56,*r3
14 02 d8 7f    
ed 31 47 05    sv.add/dw=32/ff=~RC1/sw=8 *r122,r56,*r3

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