[Libre-soc-bugs] [Bug 762] Peripheral Pin Muxing Development

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=762

--- Comment #26 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
these need to go.

 118                     with m.Else():
 119                         sync += rd_multi[i].oe.eq(0)
 120                         sync += rd_multi[i].ie.eq(0)
 121                         sync += rd_multi[i].puen.eq(0)
 122                         sync += rd_multi[i].pden.eq(0)
 123                         sync += rd_multi[i].io.eq(0)
 124                         sync += rd_multi[i].bank.eq(0)

replace with:

  93         comb += wb_rd_data.eq(Cat(*rd_multi))
  94         for i in range(len(bus.sel)):
                  sync += rd_multi[i].eq(0)


 130         # Delayed from the start of transaction by 1 clk cycle
 131         with m.If(new_transaction):
 132             # Update the GPIO configs with sent parameters
 133             with m.If(bus.we):

NO.  again, you are creating a 2-clock situation where bus.we will
be ***INVALID*** at the time new_transaction is raised.

remove new_transaction entirely.  delete ONLY the lines marked DELETE

 126         with m.Else():
 127  DELETE           sync += new_transaction.eq(0)
 128             sync += wb_ack.eq(0)
 129 
 130         # Delayed from the start of transaction by 1 clk cycle
 131  DELETE       with m.If(new_transaction):
 132             # Update the GPIO configs with sent parameters
 133  DELETE           with m.If(bus.we):


the entirety of the wishbone transaction is
***ONLY VALID AT THE CYCLE IT OCCURS***

look again at the WB4 specification PDF.  how on earth can the specification
be complied with if new_transaction is raised to indicate "please only read
wb.we on the **NEXT** cycle"??

you even say, at line 130, "delayed by 1 clk cycle" which means you are
reading the value of bus.we from the **NEXT** wishbone transaction **NOT**
the value of bus.we of the **PREVIOUS** cycle where it was valid.

bus.stb, bus.we, bus.data, bus.adr, these come as a *SPECIFIC* package
(transaction) on THAT cycle and THAT cycle alone.

look again at the timing diagrams in the WB4 spec.

yes it has taken me at least one year to fully understand this, you are
not alone in getting it wrong.  it is an absolute pig.

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