[Libre-soc-bugs] [Bug 839] SVP64 / Extra-V / ZOLC whitepaper

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=839

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i have a better version of the placeholder one with a lot of words on it.
https://ftp.libre-soc.org/20220509_161905.jpg

but because my writing is scraggly, the words are:

Loop
   Load/Inc
   TEST ZERO?
   MUL
   Store/Inc

* LOAD/STORE INC
 (Snitch Style)
* TEST-ZERO
 (EXTRA-V Style)
* LOOPS
 (ZOLC Style)

MEM   L1/L2 CPU REGFILE

MEM  PE PE-REG  L1/L2 (with a cross)   CPU   REGFILE (with a cross)

* PE runs ZOLC
  and Snitch style
* PE Sends via
  OpenCAPI to CPU,
  receives as well?

Main CPU
* OpenCAPI direct to CPU: Queues
  (Snitch Style)
* L1/L2 Not involved!
* Regfile NOT involved!
* CPU cound send direct to Memory?
  (depends on algorithm)


MEM    PE    PE Reg     CPU
                      (Coordinating
                       OpenCAPI

* CPU not idle:
  coordinating
  parallel procesing,
  Managing RADIX MMU
  of PEs


do try to also include a lot of colour in the blocks (MEM, PE, etc.):

* MEM should be one colour    (consistent)
* PE should be another colour (consistent)
* REGFILE another

etc. etc.

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