[Libre-soc-bugs] [Bug 755] add grev instruction (OP_GREV)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=755

--- Comment #54 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
nope, it's not the same. drat.  what it's missing is the inversion (XOR-effect)
of the input bits within each row.  that's what makes grevlut special.

here's what would work (roughly):

https://ftp.libre-soc.org/2022-05-17_12-17.png

* double the size of the AND-OR-INV (AOI)
* bring in an *inversion* of the A[]-straight and A[]-cross-over bits per row
* put the *inverted* copy of A[]-straight and A[]-crossover
  through the *second* set of AOIs
* arrange for sh[] to be a pass-thru which puts A[]-straight untouched
  into the output.

(this is the bit i got wrong in the diagram, if 4 AND gates are used then
 the output is always zero.  what's needed is that the imm is converted
 to be... 0b0001 which indicates "please put A[] through untouched". i think)

it would, i believe, in pseudocode, be this:

    AOI_inputs = A[i] | A[i^cross]<<1 | ~A[i]<<2 | ~A[i^cross]<<3
    AOI = (AOI_inputs & (sh[j] ? imm : 0b0001)) != 0b0000
    output[i] = AOI

it introduces one single NOT-inverter on each layer, it combines the
MUXes into one...

at each point 6x64 there are:

* 2x NOTs              - 2 gates
* 4x ANDs              - 4 gates
* 1x 4-input OR-gate   - 4? gates?

which is only 10 gates total. let's say i got it wrong and it's 20 gates.
20 * 6 * 64 = 7680 gates which is still damn good.

what about the gate-delay chain:

* gate-delay-chain is 3 gates (NOT, AND, 4-input-OR)
* that's per layer, 6 layers
* total 18 gates instead of 12 gates.

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