[Libre-soc-bugs] [Bug 755] add grev instruction (OP_GREV)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=755

--- Comment #50 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #49)

> latency of full network:
> 6 muxes through data input and 12 muxes through select input plus wire delay
> -- will almost certainly need 2 clock cycles.

perfectly fine. i've made almost everything min 3 stage ALUs because
of combinatorial paths in MultiCompALU.

> this is 3x a grev/gorc
> combined network. also 3x a rotator network.
> 
> gate count of full network:
> 4 * 6 * 64 = 1536 muxes

call it 5 gates per mux? 8000 gates. less than a multiplier by 30%.
for 256 instructions (which is what 2x 4-entry luts gives)
that's pretty damn good.  

> a grev/gorc combined network can be made by taking a grev network and
> writing it in terms of the 4-input and-or-invert cells that the muxes would
> likely be anyway, converting every other layer to or-and-invert, and then
> enabling both and-gate inputs simultaneously instead of having them be S and
> ~S.

which covers only 2 out of the possible 256 instructions of grevlut.
actually 2 out of 512 because i added an invert-input bit as well.

for less than 0.5% of instructions it's not worth the effort and
grev/gorc is nowhere near capable of generating the types of
immediates that grevluti can.

grev and gorc i don't think are worth spending any more time on.
frees up 8x X-Form instructions by removing them.

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