[Libre-soc-bugs] [Bug 834] binutils: support draft 32-bit instructions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=834

--- Comment #6 from Dmitry Selyutin <ghostmansd at gmail.com> ---
/* An XBM5 form instruction. */
#define XBM5(op, xop, rc)                       \
  (OP (op)                                      \
   | ((((uint64_t)(xop)) & 0x3ff) << 1)         \
   | (((uint64_t)(rc)) & 1))
#define XBM5_MASK       XBM5 (0x3f, 0x3ff, 1)

/* An XBM6 form instruction. */
#define XBM6(op, xop, rc)                       \
  (OP (op)                                      \
   | ((((uint64_t)(xop)) & 0x1ff) << 1)         \
   | (((uint64_t)(rc)) & 1))
#define XBM6_MASK       XBM5 (0x3f, 0x1ff, 1)

#define XBI5 SH
  { 0x1f, 11, NULL, NULL, 0 },

#define XBI6 SH16
  { 0x3f, 10, NULL, NULL, 0 },

{"grev",        XBM5(5,150,0),  XBM5_MASK,      DRAFT,  PPCVLE, {RT, RA, RB}},
{"grev.",       XBM5(5,150,1),  XBM5_MASK,      DRAFT,  PPCVLE, {RT, RA, RB}},
{"grevw",       XBM5(5,182,0),  XBM5_MASK,      DRAFT,  PPCVLE, {RT, RA, RB}},
{"grevw.",      XBM5(5,182,1),  XBM5_MASK,      DRAFT,  PPCVLE, {RT, RA, RB}},
{"grevi",       XBM6(5,214,0),  XBM6_MASK,      DRAFT,  PPCVLE, {RT, RA,
XBI6}},
{"grevi.",      XBM6(5,214,1),  XBM6_MASK,      DRAFT,  PPCVLE, {RT, RA,
XBI6}},
{"grevwi",      XBM5(5,246,0),  XBM5_MASK,      DRAFT,  PPCVLE, {RT, RA,
XBI5}},
{"grevwi.",     XBM5(5,246,1),  XBM5_MASK,      DRAFT,  PPCVLE, {RT, RA,
XBI5}},

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