[Libre-soc-bugs] [Bug 762] Peripheral Pin Muxing Development

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=762

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

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                 CC|                            |lkcl at lkcl.net

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok i did a quick video for you on how to view byte-level access,
and it points out that because the GPIO is exactly 8 bits, those
bytes map precisely and exactly to those of the wishbone bytes.

https://youtu.be/Pf6gmDQnw_4

the issue is that you don't yet fully understand wishbone "sel"
(select) lines, so haven't taken that into consideration in the
code.  the video explains "sel" lines, and explains that they
are *NOT* byte-enable-lines: the user of the wishbone bus can
in fact set a data width of 64 and a sel width of only 2, which
would be a *WORD* granularity.  sel=0b01 would be read/write to
the first 32-bits, sel=0b11 would be read/write to the TOP 32-bits
but, as i explain in the video, about 2/3-way through, this would
be Bad(tm) because each GPIO data structure is only 8-bit.

so the only wishbone configs that we should support are:

* dat_r/w = 8-bit, sel=1-bit
* dat_r/w = 16-bit, sel=2-bit
* dat_r/w = 32-bit, sel=4-bit
* dat_r/w = 64-bit, sel=8-bit

notice there that

    8<<len(sel) == len(dat_r)

therefore you can do an assert with that as a condition.

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