[Libre-soc-bugs] [Bug 196] Formal correctness proof needed for the IEEE754 FPU

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=196

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #3)
> to the smtlib2 language (the actual input language for the smt solvers --
> which supports real numbers (actually real algebraic numbers, it lacks
> transcendental ops/constants)). yosys doesn't support anything but
> bitvectors and arrays of bitvectors -- no real numbers (don't confuse it
> with yosys's partial support for verilog reals but only in parameters and
> only as literal numbers -- verilog real is a double, not a real number).

yeah even if it existed we could in no way rely on FP number
representation, it would be machine-dependent and there is
just no way it could be trusted.  even if soft-implemented
(j hauser softfloat) that's still dicey.

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