[Libre-soc-bugs] [Bug 784] Implement cl* instructions for carry-less operations

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=784

--- Comment #37 from Jacob Lifshay <programmerjake at gmail.com> ---
I implemented a FSM for cldivrem:
https://git.libre-soc.org/?p=nmigen-gf.git;a=commitdiff;h=49f1c51b676e692f1aa6964fa6e97f6af3464932

it has a parameter so you can select how many stages of the division algorithm
it does per clock cycle...allowing you to do something like set that to 4 and
have a 64-bit division take 16 clock cycles instead of 64.

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