[Libre-soc-bugs] [Bug 781] create wrapper register files around 1R-or-1W SRAMs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=781

--- Comment #12 from Cesar Strauss <cestrauss at gmail.com> ---
I'm worrying a bit about power-on initialization of the register file, when
using this wrapper.

As I understand it, on an ASIC, SRAM blocks have random data at power on, and
even the reset signal will not affect its contents.

If the register file is allowed to be undefined at power on, in the Instruction
Set Architecture, then I guess it's OK to read random data before the first
write.

However, if multi-port is implemented by copying, then, at power on, reads from
the same location will return different data, on different ports!

I mean, I guess it's OK to read random data at power on, but inconsistent
data???

Furthermore, with the LVT implementation, a write on any port will suffice to
put a register location in a consistent state.

However, with the XOR implementation, which does read/modify/write, I believe
you need to write once on *every* write port, to accomplish that.

So, do you think we should add a state machine to initialize the register file
at power on?

-- 
You are receiving this mail because:
You are on the CC list for the bug.