[Libre-soc-bugs] [Bug 829] New: Post-layout verification of ASIC SRAM blocks

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=829

            Bug ID: 829
           Summary: Post-layout verification of ASIC SRAM blocks
           Product: Libre-SOC's second ASIC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: source code
          Assignee: lkcl at lkcl.net
          Reporter: staf at fibraservi.eu
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

The blocks that will be on the router ASIC and generated by the compilers
developed in bug #828 should be verified with simulation and (estimated)
parasitics. This is for both the used 1RW and 2RW blocks.
Especially bigger block will need to be verified for race conditions on the
internal signals due to the load on the nets.
The effort needed for this exercise will depend on the number of unique blocks
and the size of the blocks.

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