[Libre-soc-bugs] [Bug 827] New: 2RW SRAM cell design; 1RW SRAM cell improvement

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=827

            Bug ID: 827
           Summary: 2RW SRAM cell design; 1RW SRAM cell improvement
           Product: Libre-SOC's second ASIC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: source code
          Assignee: lkcl at lkcl.net
          Reporter: staf at fibraservi.eu
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

For the Gigabit ASIC dual port 2RW SRAM blocks will be developed.
This task is for development of the 2RW SRAM cell. It consists of the design
and layout of the cell.
Also the 1RW SRAM cell will be visited as likely the area can be reduced with w
reduction of the transistors.

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