[Libre-soc-bugs] [Bug 795] No console output from ls2 builds

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=795

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to tpearson from comment #2)
> Confirming this issue is solved by uncommenting the "`define
> DATA_BUS_WIDTH_8" line in uart16550/rtl/verilog/uart_defines.v.
> 
> A full build on the ppc64le server followed by a test on the Raptor Versa 85
> board resulted in coldboot starting up and printing correct data to UART as
> expected.

unnnbelievable. about frickin time that was found.
microwatt "solved" this by having a local copy of the
HDL.

basically we need automated setup. which was always the plan,
but time pressure is getting in the way.

do you happen to know how to set defines *without* altering
the source code? icarus verilog which is an emulator has "-D XXXX"
just like in c.

i don't know if that's possible with yosys or if it is possible
to create a define in another file that is picked up by all .v
files? (are defines global in other words)

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