[Libre-soc-bugs] [Bug 781] create wrapper register files around 1R-or-1W SRAMs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=781

--- Comment #7 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Staf Verhaegen from comment #6)
> I think the problem is in the "Live Value Table". I don't see how you can
> live with a 1RW block there ?

Indeed, it will be a plain 1W1R FFRAM, but only 1-bit wide, per write lane.

We could try to get rid of the LVT, using the XOR trick (as described in
http://people.csail.mit.edu/ml/pubs/trets_multiport.pdf).

It should involve adding another half-duty-cycle read port, I think, making it
50% larger (6 x 1RW blocks).

I suppose it will start making sense for larger memories and/or more read
ports, where a deep multi-port FFRAM LVT will cost more.

This is of course assuming we won't have a dual port memory block available,
otherwise all this exercise is moot, I guess.

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