[Libre-soc-bugs] [Bug 781] New: create wrapper register files around 1R-or-1W SRAMs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=781

            Bug ID: 781
           Summary: create wrapper register files around 1R-or-1W SRAMs
           Product: Libre-SOC's second ASIC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: source code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

base-level SRAMs are 1R or 1W, this is a hard limitation of the
way the cells are designed.  addressing can be provided to give
multiple banks and multiple rows but with every single cell being
1R *or* 1W, the entire (larger) SRAM is also so limited.

register files obviously need much more than a single read port
or a single write port and they need a bare minimum of 1R *and*
1W on the *same* clock cycle.  this can be provided (in effect)
by running at Double Data Rate where on one edge is 1x Read and
on the other is 1x write.

on top of that DDR block, a *second* trick is to have multiple
such SDRAMs, write to all of them and allow independent reads.

both these things need doing

-- 
You are receiving this mail because:
You are on the CC list for the bug.