[Libre-soc-bugs] [Bug 763] Work on I/O Core Pad JTAG Tests

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=763

--- Comment #3 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
Based on your reply, I looked at yesterday's waveforms and saw the Capture
state happens before the Shifting state (when the BS data or JTAG configuration
is shifted in), but as I was about to start running the code again, I got an
assertion error from c4m-jtag tap.py.

https://git.libre-soc.org/?p=c4m-jtag.git;a=blob;f=c4m/nmigen/jtag/tap.py;h=e0cf747150c03c45a7be16682b31422103ab75bc;hb=eb28aea69c7a785085364c2fb3c2cbdbe86f4890#l592
(assertion on #l616)

The assertion fails because the length of iol does not match the sum of all
subsignals in _ios:
Traceback (most recent call last):
  File "testing_stage1.py", line 1005, in <module>
    test_jtag()
  File "testing_stage1.py", line 976, in test_jtag
    dut = setup_blinker(build_blinker=False)
  File "testing_stage1.py", line 930, in setup_blinker
    vl = rtlil.convert(top, ports=top.ports())
  File "/home/rohdo/src/nmigen/nmigen/back/rtlil.py", line 1054, in convert
    fragment = ir.Fragment.get(elaboratable, platform).prepare(**kwargs)
  File "/home/rohdo/src/nmigen/nmigen/hdl/ir.py", line 37, in get
    obj = obj.elaborate(platform)
  File "/home/rohdo/src/nmigen/nmigen/hdl/dsl.py", line 538, in elaborate
    fragment.add_subfragment(Fragment.get(self._named_submodules[name],
platform), name)
  File "/home/rohdo/src/nmigen/nmigen/hdl/ir.py", line 37, in get
    obj = obj.elaborate(platform)
  File "/home/rohdo/src/soc/pinmux/src/spec/jtag.py", line 185, in elaborate
    m = super().elaborate(platform)
  File "/home/rohdo/src/c4m-jtag/c4m/nmigen/jtag/tap.py", line 434, in
elaborate
    bd2io=io_bd2io, bd2core=io_bd2core,
  File "/home/rohdo/src/c4m-jtag/c4m/nmigen/jtag/tap.py", line 621, in
_elaborate_ios
    assert idx == length, "Internal error, length mismatch"
AssertionError: Internal error, length mismatch

Adding prints to tap.py show me that self._ios is a list of records, each
record containing a core/pad pair:
[(rec uart_0__rx (rec uart_0__rx__core i) (rec uart_0__rx__pad i)),
... more signals ...
(rec i2c_0__scl__oe (rec i2c_0__scl__oe__core o) (rec i2c_0__scl__oe__pad o))]
So, the total number of subsignals in _ios is 40.

iol is a list that *only* contains peripheral core outputs and pad inputs (i.e.
signals that JTAG cannot control, but can only sample):
[(sig uart_0__rx__pad__i), (sig uart_0__tx__core__o), 
... more signals ...
(sig i2c_0__scl__i__pad__i), (sig i2c_0__scl__o__core__o), (sig
i2c_0__scl__oe__core__o)]
No pullups/downs or banksel are requested on any of the pins, so that part of
the code in tap.py is not being used. Total number of subsignals in iol is 20.

I was wondering whether the chain is meant to be 40 bits long (to account for
the core/pad pair), but I don't understand it enough to make that conclusion.

The way the code shows it (and the way you described it) indicates that theres
a (not including intermediate states like idle, run, etc.):
1. shifting stage (which I've seen in the waveforms)
2. update stage where signals controlled by JTAG BS are set by the shift
register
3. capture stage where JTAG inputs are copied into the main shift register

So that implies there's no need for a 40-bit chain, as you can access the
inputs and outputs by selecting different modes.

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