[Libre-soc-bugs] [Bug 755] add grev instruction (OP_GREV)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=755

--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #26)

> no, it's a bug in the simulator that there isn't a way to request RC without
> OE

this really is not a bug, it's a [annoying] design decision. totally 
undocumented and "emergent", but not something that is unexpected.

if there are going to be multiple Rc=1 but not OE=1 new Logical
instructions then yes i think thst justifies sorting out.

to keep compatibility i suggest adding a new RC option, called say
RCONLY which will need to be added to DecodeRC and to ISACaller,
and possibly the pipelines common_input.py and several other places.
decode_regspec_map will need inspecting too.

all pipeline, compunit and several issuer unit tests will need to
be run to make absolutely sure no damage is done.

it's not a "minor job" in other words.  if you're going to tackle it
for goodness sake don't push/commit anything without running a
massive set of unit tests.  use a branch if you like, it's justifiable

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