[Libre-soc-bugs] [Bug 762] Peripheral Pin Muxing Development

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=762

--- Comment #2 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
After conversation with Luke on IRC yesterday
(https://libre-soc.org/irclog/%23libre-soc.2022-01-14.log.html), came up with
the following improvements:

- Get rid of multiple addresses for CSR, output, and input access. Instead
reading input or writing output will happen when reading/writing the GPIO
configuration. -- IMPLEMENTED
- Condense the configuration word from 16-bits down to 8-bits: 
bank1 bank2 bank3 InOutBit | PD PU IE OE -- IMPLEMENTED
- Fit multiple GPIO configurations in a single WB transaction (depends on the
width of the WB bus) -- NOT DONE YET
- Add a multiplexer which switches over GPIO configuration control from WB bus
to other peripherals when bank_select is changed. -- NOT DONE YET

This is the current code:
https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/simple_gpio.py;hb=714f30b9eb0f49f68faedb111a5bdc22b7e7b610

The sim is working, however there are no asserts yet, and I'm working some test
pattern function to exercise more of the block (instead of setting everything
to out etc.).

Also will update the documentation describing the GPIO block (still same link
as in comment #0).

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