[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #33 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Cesar, i thought through some ideas, and if you pass the signal core.busy_o
globally back to fetch, that will be sufficient.

Fetch FSM:

      if not core.busy_o:
          n.data.insn = fetched_insn
          n.o_valid = 1

Decode Phase:

      if not core.busy_o
         same thing

in other words core.busy_o is the global stall condition.

in this way it will be really simple and easy to do.

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