[Libre-soc-bugs] [Bug 630] Skywater 130nm PDKMaster

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=630

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #8)

> This is my test design for IO; as always I had hoped to do a little more
> simulation on the performance side so the design is likely sub-optimal. But
> at least we have something that can be used to verify design and as base for
> optimization later.

yes. nice to have the chance to test things at all, esp. on such a quick
iteration (and not need to pay for them!)

> So I think the state of the subtasks is then as follows:
> * Sky130 technology setup in PDKMaster: 100%
> * Port and optimization of c4m-flexcell: 70%
> * Port and adaption of c4m-flexio (125MHz digital IO target): 90%
> * Port of c4m-flexmem; complete single port compiler: 20%

i've just started running linux (with virtual memory) in simulations,
that gives L1 caches, which are (per cache, i.e. D-Cache and I-cache),
they are quite small so as not to take up huge resources:

* QTY 1of 16x 192-bit (24 byte per row), for cache tags, total 384 bytes
* QTY 4of 128x 64-bit (8 bytes per row), for actual data, total 4x 1024 bytes

so, per cache, there are *five* SRAM blocks per L1 cache:
one of 384 bytes, four at 1k.  they are also 1R *OR* 1W, rather
than "simultaneous support on the same clock for 1R AND 1W"
(i remember you said that makes a big difference)

i *may* have time to reorganise those into something more "normal", however
getting the microwatt-ported dcache/icache code running has taken almost a
year so it is... unwise, shall we say, to mess with it.

the microwatt I-cache is designed to be 1 cycle delay (read-en on one clock, 
data appears on the next), but interestingly - and this is more for FPGAs than
ASICs - a *two* cycle delay was added by the microwatt team to the D-Cache.
that can be handled with putting an external latch in front of the (exact
same cell) same SRAM used for I-Cache.

i remember seeing somewhere that the 2-clock delay on D-Cache is to be
able to meet Xilinx FPGA BRAM rules. but, the microwatt design is so
complex (the 2-cycle delay is embedded into the HDL) that i don't want to
alter it.


> In the coming weeks I will focus on the following things:
> - complete c4m-flexcell conversion
> - memory block for mpw5
> - stabilize PDKMaster API so it will finally become possible to accept
> external contributions

brilliant to hear.

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