[Libre-soc-bugs] [Bug 630] Skywater 130nm PDKMaster

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=630

--- Comment #8 from Staf Verhaegen <staf at fibraservi.eu> ---
There has been two designs committed for Sky130 based on the port:
1) https://efabless.com/projects/600
For this project I delivered the standard cells using c4m-flexcell and my
Sky130 port of PDKMaster. Myrtle provided the RTL and then Myrtle and Jean-Paul
cooperated on the Coriolis P&R. The conversion of c4m-flexcell is only partial
complete at the moment but plan is to 
2) https://efabless.com/projects/621
This is my test design for IO; as always I had hoped to do a little more
simulation on the performance side so the design is likely sub-optimal. But at
least we have something that can be used to verify design and as base for
optimization later.

So I think the state of the subtasks is then as follows:
* Sky130 technology setup in PDKMaster: 100%
* Port and optimization of c4m-flexcell: 70%
* Port and adaption of c4m-flexio (125MHz digital IO target): 90%
* Port of c4m-flexmem; complete single port compiler: 20%

In the coming weeks I will focus on the following things:
- complete c4m-flexcell conversion
- memory block for mpw5
- stabilize PDKMaster API so it will finally become possible to accept external
contributions

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