[Libre-soc-bugs] [Bug 911] svshape2 instruction (with offsets)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=911

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #5)
> (In reply to Luke Kenneth Casson Leighton from comment #4)
> > (In reply to Jacob Lifshay from comment #1)
> > > notes: offset will need to be signed.
> > 
> > this makes me jittery as it is an extra bit.  at least 3 bits are needed
> > to be able to offset to a byte within a 64 bit register.  now it is 4 bits,
> > they are very precious in SVSTATE. i think there is room.
> 
> assuming you meant SVSHAPE0-3, not SVSTATE.

... yes.

> imho it'd make more sense to just expand SVSHAPE0-3 to 64-bits...

no, because i kept them very specifically to 32 bit so as to reduce
context switch latency.  on the TODO list is to merge into 1/2 the number
of 64 bit SPRs.

> we'd want
> more than i4 for offset, since many instructions can only access every other
> or every 4th register iirc, so offset should be able to cover the rest of
> the bytes.

future version.

> also, it just occurred to me we don't need signed offset after all, e.g. if
> you want offset -2 for bytes, just use offset -2 % 8 = 6 instead and use the
> previous register in the sv.* instruction.

face-palm moment, of course. i still have 4 bits anyway because of VSX 128-bit
registers (quad.prevision, not the SIMD ones)

> rather than:
> svshape2 offset=-1, remap=ra
> sv.add/elwid=8 *32, *64, *32
> 
> do:
> svshape offset=6, remap=ra
> sv.add/elwid=8 *32, *63, *32
> 
> or:
> svshape offset=14, remap=ra
> sv.add/elwid=8 *32, *62, *32 # if you can't address every register...

neat. like it.  that fixes the EXTRA2 problem. like it.

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