[Libre-soc-bugs] [Bug 825] New: Add a new parser/driver able to handle Verilog names

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=825

            Bug ID: 825
           Summary: Add a new parser/driver able to handle Verilog names
           Product: Libre-SOC's second ASIC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: source code
          Assignee: lkcl at lkcl.net
          Reporter: Jean-Paul.Chaput at lip6.fr
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

Currently, Coriolis can only read/write netlist in:

* BLIF, which is completely obsolete and is used *only* because
  it was quicker than to develop a Verilog parser.

* VST, the Alliance VHDL subset, which cannot handle all the valid
  characters in Verilog so we must perform a name mangling which
  muddies the netlist.

To solve that, add a new parser driver so we can directly support
Verilog names. We should choose among the following candidates:

* Verilog (simplified version for netlist) for obvious reasons.
* RTLIL, as the native output format of Yosys, but not ideal for
  other ones.
* FIRRTL
  https://github.com/chipsalliance/firrtl/blob/master/spec/spec.pdf

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