[Libre-soc-bugs] [Bug 762] Peripheral Pin Muxing Development

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=762

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|lkcl at lkcl.net               |andrey at technepisteme.xyz

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
wotcha andrey, as we discussed yesterday:

 112         with m.If(bus.cyc & bus.stb):
 113             comb += wb_ack.eq(1) # always ack

that needs to be a sync

 112         with m.If(bus.cyc & bus.stb):
 113             sync += wb_ack.eq(1) # always ack, always delayed

then what you can do here is:


 125                 for i in range(0, self.wordsize):
 126                     multi_cat.append(rd_multi[i])
 ...->               with m.If(wb_ack):
 127                     comb += wb_rd_data.eq(Cat(multi_cat))


but that would get the data a clock-cycle late, so how about:

        # One address used to configure CSR, set output, read input
        with m.If(bus.cyc & bus.stb):
            sync += wb_ack.eq(1) # always ack but on next cycle
            # Concatenate the GPIO configs that are on the same "row" or
            # address but do NOT send...
            multi_cat = []
            for i in range(0, self.wordsize):
                multi_cat.append(rd_multi[i])
            sync += wb_rd_data_reg.eq(Cat(multi_cat))
            with m.If(bus.we): # write
                ...

            # ok NOW send it! (but on the ack'd cycle)
            with m.ElIf(wb_ack): # read (and acked)
                comb += wb_rd_data.eq(wb_rd_data_reg)

btw this will look dreadful in the graphviz (and be costly):

            for byte in range(0, self.wordsize):
                sync += multi[byte].eq(wb_wr_data[byte*8:8+byte*8])

suggest doing a Cat() trick as well on that.

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