[Libre-soc-bugs] [Bug 724] Determine required memory compiler developments

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=724

Staf Verhaegen <staf at fibraservi.eu> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   budget (EUR) for|2000                        |1000
         this task,|                            |
          excluding|                            |
   subtasks' budget|                            |
       The table of|"Staf Verhaegen" = 2000     |"Staf Verhaegen" = 1000
  payments (in EUR)|                            |
     for this task;|                            |
        TOML format|                            |
 total budget (EUR)|2000                        |1000
  for completion of|                            |
       task and all|                            |
           subtasks|                            |

--- Comment #25 from Staf Verhaegen <staf at fibraservi.eu> ---
As deadline for Gigabit ASIC is approaching fast the time for new SRAM
development is limited. In order to possiblity of tape-out in the NGI Pointer
time frame it was decided to go for a dual port 2RW design and make wrappers
for all needed blocks like registers files (3R1W etc).

Reason to go for dual port 2RW block is that blocks from the single port 1RW
SRAM can be reused and this way the dual port can be fitted in the timeframe of
this project. The 1RW cell has one bit line pair and the 2RW cell has two bit
line pairs. The reading and writing of each of the two bit line pairs can be
done with the same circuits as for the single port compiler. Due to the higher
load on the bit cell when reading on the two ports at the same time the design
of the 2RW cell may end up in a relatively bigger SRAM cell though.

If one would use a 10T 2R1W cell the reading and the writing has to be done
with other circuits and thus involve more work. Also the 2RW is more versatile
as it can for example easily be used as cache or it can be used as a 1R1W block
and form there make a 2R1W wrapper around it.

As the scope of this investigation is now reduced due to time pressure also the
budget for this task is reduced.

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