[Libre-soc-bugs] [Bug 630] Skywater 130nm PDKMaster

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=630

Staf Verhaegen <staf at fibraservi.eu> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|CONFIRMED                   |RESOLVED
         Resolution|---                         |FIXED

--- Comment #11 from Staf Verhaegen <staf at fibraservi.eu> ---
Update to this task.

I got seriously delayed on this task due to bug fixing I had to do. For MPW4
some bugs were seen and plan was to fix these in a week or two before
continuing with these. The actual bug fixing took more than 6 weeks. The bug
fixing itself is on budget of another project
(https://nlnet.nl/project/AMSL/index.html) but it caused a serious delay for
this task.

When I was ready to continue development on this task Sky130 MPW5 was already
pretty close so I focused on preparing a design for tape-out there.
* Project page: https://platform.efabless.com/projects/739
* gitlab repo: https://gitlab.com/Chips4Makers/sky130mpw5-sramtest
Unfortunately the design went not through the lottery and was thus not part of
MPW5. It did have single port on the design so the c4m-flexmem part of this
task is considered to be finished. There is still some work to fully finish the
single port compiler but this will be done combined with the dual port
compiler.

The port of the standard cells was also done and used in another MPW5 tape-out
(https://platform.efabless.com/projects/691). Luckily this design was on MPW5.

In the mean time I also prepared a follow-up to my MPW4 IO test tape-out. This
was a proposal from efabless to have the IO cells taped using wire-bonding. On
MPW4 I had to remove the pad opening on the IO cells to avoid shorts with the
redistribution (RDL) layer.
I targeted this design for ChipIgnite3 but due to changing circumstances @
efabless this likely also has to move to later tape-out.
* Project page: https://platform.efabless.com/projects/821
* gitlab repo: https://gitlab.com/Chips4Makers/sky130chipign3-iotest
With this design done also the work in this task on IO cells is completed.

So with all these designs this task is completed.

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