[Libre-soc-bugs] [Bug 808] ICache module unconditionally accepts Wishbone ACK

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=808

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |INVALID
             Status|CONFIRMED                   |RESOLVED

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
declaring this one invalid because WB3 classic master cannot drive WB4 pipe
slave.

WB4 Pipe stb *has* to be behind WB4 pipe ack (by at least 1 clock) where if
stall is set it will be longer than 1 clock.

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