[Libre-soc-bugs] [Bug 812] invalid access to 0x0 on startup leads to core hang

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=812

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
still a mess but a working mess.

added an extra reset delay counter to ECP5CRG which is *separate* from
the 25 mhz "init" clock domain.

this allows different reset releases which is ok.

better design would be to trigger them in a cascade. later.

also added in a single cycle delay *in the core* which gives time
for reset pc to get into the fetch FSM.

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