[Libre-soc-bugs] [Bug 812] New: invalid access to 0x0 on startup leads to core hang

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=812

            Bug ID: 812
           Summary: invalid access to 0x0 on startup leads to core hang
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Other
            Status: CONFIRMED
          Severity: major
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: tpearson at raptorengineering.com
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

With the current ls2/soc/nmigen versions, the CPU core reset appears to be
overridden by the default nmigen soc reset, and both resets appear to be
released at the same time.

This has the net effect of holding the CPU PC at 0x0 instead of <RESET_VECTOR>
during the reset pulse.  When the CPU reset and SoC resets are released
simultaneously, the ICache sees the 0x0 PC for an instant and starts loading a
cache line from 0x0.  This locks up the bus since nothing responds to the
requests for 0x0, 0x8, etc.

I am working on staggering the main rst pulse and the CPU reset pulse to fix
this problem.

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