[Libre-soc-bugs] [Bug 806] Nest should be able to run at different clock rate than main CPU

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=806

--- Comment #23 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to tpearson from comment #21)

> On deeper investigation, it looks like the DomainRenamer may do what we need
> here.

wheww :)

> However, the gram tree right now contains a bunch of instances of
> "dramsync".  From where I sit we need to change those back to "sync" so that
> the renamer is consistent, it's just plain confusing at the moment and I
> think this was the origin of some of my misconceptions...

well... ultimately, they should in fact be different, because when
the ASync-ness is moved down into GRAM *itself*, it would be *GRAM*
that... ah yes and it would also use DomainRenamer :)

wark-wark

let me try that again.  there are 3 components in GRAM

* grambone (WB-to-DFII)
* gramcore (DFII-to-PHY)
* gramphy  (PHY-to-IOpads of the ECP5)

we're going to put *all* of those into a 100 mhz clock domain
called dramsync, with a 2x domain to run the IOPads on 4-phase
(xdr=4)

then, ASyncWBBridge will front the cross-over from 40mhz (whatever)
in the "sync" domain to 100mhz (whatever) of GRAM.

what *actually* needs to happen is:

* grambone runs in the *nest* clock domain (aka the cpu)
* gramcore needs to have its *OWN* ASync FIFOs (not wishbone, at all)
           these FIFOs are at the *DFI command* level
* gramphy  stays at it is (100 mhz, dramsync)

something like that.  it's not straightfoward, at all, but it basically
reduces the amount of crap that has to be run in GRAM at the highest
clock frequency.

if the only thing running in GRAM at the higher clock frequency is the
gramphy and that's connected directly to Async FIFOs i see no reason why
attempts should not be made to run the PHY at 150-200 mhz.

but

i am getting way ahead.

right now the primary task is to decouple the "entirety-of-GRAM" to
get it, as a single job-lot, to run at 100 mhz.

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