[Libre-soc-bugs] [Bug 806] Nest should be able to run at different clock rate than main CPU

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=806

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=ls2.git;a=blob;f=src/ecp5_crg.py;h=36c8f1dd4f5ecde53a30f8b949862abfdb828117;hb=2d7021ba09c3e08e1780bf73c26deeaccf689221


see dramsync at the bottom.

dramsync speed as a parameter dram_freq is
supposed to be passed in (not a new frequency
and a new domain called "cpu")

the plans i had in mind were that if dram_freq is
None then dramsync.eq(sync) making them the same
otherwise add a new call

not

 240         else:
 241             pll.create_clkout(ClockSignal("cpu"), self.core_clk_freq)

this

 240         else:
 241             pll.create_clkout(ClockSignal("dramsync"), self.dram_clk_freq)

remove cpu freq remove replacement clk_freq core_freq less disruptive
patch add one line "dram_freq"

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