[Libre-soc-bugs] [Bug 808] New: ICache module unconditionally accepts Wishbone ACK

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=808

            Bug ID: 808
           Summary: ICache module unconditionally accepts Wishbone ACK
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Other
            Status: CONFIRMED
          Severity: minor
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: tpearson at raptorengineering.com
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

The ICache module appears to unconditionally accept all ACKs from the connected
Wishbone slave and treat them as valid data transfers, even if the bus is in a
STALL state.

I am unclear as to whether this is intentional, but it does mask specific types
of non-compliancy in connected peripherals, e.g. that seen in bug 807.

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