[Libre-soc-bugs] [Bug 807] New: WB64to32Convert spurious ACK during master STALL in burst transfer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=807

            Bug ID: 807
           Summary: WB64to32Convert spurious ACK during master STALL in
                    burst transfer
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Other
            Status: CONFIRMED
          Severity: normal
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: tpearson at raptorengineering.com
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

The WB64to32Convert module does not obey a master stall request during burst
transfers per the Wishbone specification.  When the master attempts to stall
the slave during a burst transfer, the slave may attempt to send one beat of
data (a single spurious ACK) before finally recognizing the master is in a
STALL condition.  If this happens, the data transfer to the master is lost /
corrupted for compliant masters.

Unfortunately, a second bug in the Icache module has masked this problem, and
it took a while to figure out why inserting a new bridge controller between the
ICache and the WB64to32Convert wasn't working.

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