[Libre-soc-bugs] [Bug 805] gram randomly comes up in an unworkable condition

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=805

--- Comment #2 from tpearson at raptorengineering.com ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> (In reply to tpearson from comment #0)
> 
> > The ECP5 relies on a single master reset wire, shared among all DDR
> > primitives in a specific logical controller, to synchronize the interface
> > blocks at startup.  While this reset wire has been plumbed to the data I/O
> > blocks, it is absent from the address / command blocks where it is hardwired
> > by nmigen to 0. 
> 
> urrr.
> 
> do you happen to know of any other implementation thst gets this right?
> if i have something to work from i can take a look.

LiteDRAM gets it right:

https://github.com/enjoy-digital/litedram/blob/15f7ba27138367f21832e5c00e7882db8a6fab54/litedram/phy/ecp5ddrphy.py#L229

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