[Libre-soc-bugs] [Bug 805] New: gram randomly comes up in an unworkable condition

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=805

            Bug ID: 805
           Summary: gram randomly comes up in an unworkable condition
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Other
            Status: CONFIRMED
          Severity: major
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: tpearson at raptorengineering.com
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

The current implementation of gram is bistable, with a working state and a
non-working state, randomly entered at FPGA clock tree reset.  If the FPGA
enters the working state, memory access are reliable until another reset (or
reprogram) is issued, at which point the device has a 50% chance to enter the
non-working state.  Similarly, in the non-working state the device has a 50%
change of entering the working state on reset / reprogram.

After significant debugging effort, the root cause of this has been located.

In an nutshell, the DDR3 interface blocks require two aligned clocks, the ECLK
(DDR clock) and SCLK (SDR clock).  In the working state, the transmitter blocks
are aligned with the receiver blocks, and in the non-working state they are
misaligned by 1T (1 ECLK period, or 1/2 SCLK period).

The ECP5 relies on a single master reset wire, shared among all DDR primitives
in a specific logical controller, to synchronize the interface blocks at
startup.  While this reset wire has been plumbed to the data I/O blocks, it is
absent from the address / command blocks where it is hardwired by nmigen to 0. 
This means the address / command generator can be up to 1/2 SCLK out of
alignment with the rest of the system, and this unwanted phase delay is
randomly applied at startup from analog stochastic behavior.

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