[Libre-soc-bugs] [Bug 781] create wrapper register files around 1R-or-1W SRAMs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=781

--- Comment #8 from Cesar Strauss <cestrauss at gmail.com> ---
Things are going according to plan.

1) Simulation model of a transparent synchronous 1RW memory block in nMigen:

Code:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/sram_wrapper.py;hb=332653c94f0e6369fa8d96087a7e392430a10daf#l28

Test case waveforms:

python ~/src/soc/src/soc/regfile/sram_wrapper.py
SinglePortSRAMTestCase.test_sram_model
gtkwave test_sram_model.gtkw

2) Wrapper around two 1RW memory blocks, allowing an independent read port,
even if the write port still works only on even (or odd) cycles.

Code:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/sram_wrapper.py;hb=332653c94f0e6369fa8d96087a7e392430a10daf#l233

Test case waveforms:

python ~/src/soc/src/soc/regfile/sram_wrapper.py
PhasedDualPortRegfileTestCase.test_phased_dual_port_regfile
gtkwave test_phased_dual_port_1_transparent.gtkw

Both were formally verified, giving more confidence than just a few targeted
test cases.

Next is implementing a full 1W/1R regfile, with four 1RW memories and a LVT.

Later, we can go back to the original plan of double clocking a single 1RW
memory, but at least we will have a choice of a safer fallback, if needed.

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