[Libre-soc-bugs] [Bug 796] New: Tercel SPI PHY POR reset fails under certain conditions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=796

            Bug ID: 796
           Summary: Tercel SPI PHY POR reset fails under certain
                    conditions
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Other
            Status: CONFIRMED
          Severity: normal
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: tpearson at raptorengineering.com
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

Under specific conditions with a short (relative to SPI clock) power on reset
pulse, the Tercel SPI controller PHY may fail to reset, leading to undefined
behavior until an external reset is triggered.

This is fixed in GIT hash bf4f580 (microwatt).

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