[Libre-soc-bugs] [Bug 698] ls180 ASIC test tasks

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=698

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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                 CC|                            |staf at fibraservi.eu

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
here is the diagram for the pinouts, it was auto-generated
by the pinmux program

     https://libre-soc.org/180nm_Oct2020/ls180.svg

* the IO rail is 3.3v
* the core rail is 1.8v
* P_SYS_PLLCLK (N29) is a *digital* input clock (can be generated by FPGA
  or by signal generator)
* the P_SYS_CLKSEL_0 (N30) and P_SYS_CLKSEL_1 (N31) if set LO
  will route the digital input clock directly to sys_clk

JTAG can be done by openocd using an FT232, configuration setup description
and options are here:

     https://libre-soc.org/HDL_workflow/ECP5_FPGA/

we colour-coded the FT232 pins:

     https://libre-soc.org/HDL_workflow/ft232.png

there is "firmware upload" software written in python that connects
to jtagremote (openocd can be put into "jtagremote" mode):

   
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/firmware_upload.py;hb=HEAD

there is more in that same directory.

and there is openocd commands for running some rudimentary SVF files
and also openocd.cfg for using with FT232 

https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=openocd_ft232.cfg;h=a30c1a40748e1c34faf40ccc7601b3c1eda0fd4d;hb=b55917aafa6bbc9f16e1d97dc095e929c31aa81a

https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=README.txt;h=56adddf762d1ef5673a41e3fca87acd9263c9a34;hb=b55917aafa6bbc9f16e1d97dc095e929c31aa81a

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