[Libre-soc-bugs] [Bug 698] ls180 ASIC test tasks

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Oct 27 12:26:06 BST 2021


Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
                 CC|                            |staf at fibraservi.eu

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
here is the diagram for the pinouts, it was auto-generated
by the pinmux program


* the IO rail is 3.3v
* the core rail is 1.8v
* P_SYS_PLLCLK (N29) is a *digital* input clock (can be generated by FPGA
  or by signal generator)
* the P_SYS_CLKSEL_0 (N30) and P_SYS_CLKSEL_1 (N31) if set LO
  will route the digital input clock directly to sys_clk

JTAG can be done by openocd using an FT232, configuration setup description
and options are here:


we colour-coded the FT232 pins:


there is "firmware upload" software written in python that connects
to jtagremote (openocd can be put into "jtagremote" mode):


there is more in that same directory.

and there is openocd commands for running some rudimentary SVF files
and also openocd.cfg for using with FT232 



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